Curriculum Vitae

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Education

Research Interests

Selected Projects

FPGA-Based Design for Testability

Designed scan chains, LFSR/MISR-based BIST, and fault injection in Verilog; verified on FPGA. Outstanding thesis.

Automated IC Testing on ATE

End-to-end workflow from datasheet analysis to test-vector generation. National Second Prize, 9th National IC Competition.

Honors

Skills

Last updated: August 2026.